Static semiconductor storage device

ABSTRACT

A static semiconductor storage device is described. This device includes a plurality of word lines, a plurality of first and second bit lines and memory cells. The word lines extend in a row direction. The first bit lines extend in a column direction. The second bit lines extend in the column direction and are paired. The memory cells are connected to the word lines by each row as well as to the pairs of second bit lines by each column. The memory cells of the same column share the first bit line and are controlled to electrically couple with the second bit line thereof at different times.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2003-296414, filed on Aug. 20,2003, the entire contents of which are incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a static semiconductor storage device,and more particularly to a static semiconductor storage device includingmemory cells of transistors.

BACKGROUND OF THE INVENTION

A static random access memory (hereinafter, referred to as SRAM) isknown as a type of static semiconductor storage devices.

In SRAMs, memory cells having, for example, six transistors, are arrayedin rows and columns. These memory cells are connected to a plurality ofword lines extended in a row direction and to a plurality of pairs ofbit lines extended in a column direction. The transistors paired toconstitute each memory cell are cross connected and connected to the bitlines. In addition, nodes of these transistors are connected to a pairof switching transistors, which are connected to the word line.

When a large number of memory cells are connected to a pair of bit linesin the column direction, the bit lines are loaded with capacitance.Accordingly, a sense amplifier amplifies very small amplitude of anoutput signal from the selected pair of bit lines, in order to read outdata stored in the selected memory cell.

The sense amplifier is required to have a sufficiently low input offset,in order to sense the very small amplitude for high-speed readoutoperation. In order to achieve this, an area of the sense amplifier mustbe enlarged.

However, an influence of the dispersion of characteristics of eachelement becomes more serious as the devices are miniaturized. As aresult, it is gradually becoming difficult to produce a sense amplifierwith a sufficiently small input offset.

Thus, instead of sensing the very small amplitude, it is considered toreduce the number of the memory cells connected to each pair of bitlines in the column direction, to lighten the capacitive load of the bitlines. For this purpose, the bit lines are divided in the columndirection to read out data from each divided pair of the bit lines.

In an SRAM of single-end sensing type, each memory cell is connected toa pair of local bit lines. Furthermore, the pair of local bit lines isconnected to a pair of global bit lines through switching transistors.One of the pair of local bit lines is connected to a sense amplifier tobe used for single-end sensing.

For example, the sense amplifier to be used for the single-end sensingincludes an inverter circuit connected to the local bit lines, and ann-channel transistor having a gate connected to the inverter circuit.Such an SRAM is referred to as single-end sensing type.

The switching transistors of the memory cell are conductive by besetting the word lines to level 1 to read out data. Accordingly, thememory cell is electrically coupled with the pair of local bit lines. Inan SRAM of the single-end sensing type, capacitance of each pair oflocal bit lines is sufficiently low. Therefore, data stored in thememory cell can be outputted by increasing the electric potential of oneof the pair of local bit lines in full range from earthed potential (0V)to power supply potential (VDD).

Accordingly, when reading out data stored in the memory cell, the signalfrom the memory cell can be sufficiently amplified by a logic gate suchas an inverter circuit to sense the data.

In the case where the output of one of the selected pair of local bitlines is level 0, the n-channel transistors of the sense amplifier areconductive, and global bit lines are forced to be level 0 when readingout the data from the memory cell.

On the contrary, when the output of one of the selected pair of localbit lines is level 1, the n-channel transistors of the sense amplifierare nonconductive. Since the initial settings of the global bit linesare pulled up, level 1 is outputted from the global bit lines.

As described above, it is unnecessary to provide a sense amplifier withan input offset reduced by enlarging its area in the SRAM of thesingle-end sensing type, unlike normal SRAMs. Thus, it is possible tosubstitute a logic gate such as an NAND circuit or an inverter circuitwith a small area for a sense amplifier as described in Kevin Zhang, KenHose, Vivek De, and Borys Senyk et al, “The Scaling of Data SensingSchemes for High Speed Cache Design in Sub-0.18 μm Technologies,” 2000symposium on VLSI Circuits Digest of Technical Papers, P.226-227.

To write data into the SRAM of the single-end sensing type, one of thepulled-up pair of local bit lines connected to the memory cell becomeslevel 0. As a result, each pair of the global bit lines is required toexist for each pair of the local bit lines.

A plurality of these pairs of global bit lines are usually wired by useof upper layer metal. When a large number of the global bit lines arewired, pitches are reduced between the lines. Accordingly, capacitanceis increased between the lines. Furthermore, to prevent the pitchesbetween the lines from reducing, widths between the lines may benarrowed. However, resistance of the lines themselves increases.

These factors incur increase in wiring delay in the global bits linesand reduce the operation speed.

SUMMARY OF THE INVENTION

One aspect of the static semiconductor storage device of the presentinvention comprises:

-   -   a plurality of word lines extended in a row direction;    -   a plurality of first bit lines extended in a column direction,        the plurality of first bit lines including i-th, j-th and k-th        first bit lines (i, j and k are different arbitrary positive        integers);    -   a plurality of pairs of second bit lines extended in the column        direction, the second bit lines including i-th, j-th and k-th        pairs of second bit lines respectively corresponding to the        first bit lines;    -   a plurality of memory cells respectively arrayed in the row and        column directions and connected to the word lines by each row        and to the pairs of second bit lines by each column, each of the        memory cells having a plurality of transistors cross connected;    -   a plurality of sense amplifiers being used for single-end        sensing, each of the sense amplifiers having an input terminal        connected to one of each pair of the second bit lines, and        having an output terminal connected to each of the first bit        lines;    -   a plurality of pairs of write column switches respectively        connected between the first bit lines and the pairs of second        bit lines, the write column switches including an i-th pair of        write column switches connected between the i-th first bit line        and one of the i-th pair of the second bit lines corresponding        to the i-th first bit line, and between the j-th first bit line        and the other of the i-th pair of the second bit lines and the        write column switches further including a j-th pair of write        column switches connected between the j-th first bit line and        one of the j-th pair of the second bit lines corresponding to        the j-th first bit line, and between the k-th first bit line and        the other of the j-th pair of the second bit lines; and    -   a write controller to control conduction of the plurality of        pairs of the write column switches, the write controller        including a write controller to control the i-th pair of write        column switches and the j-th pair of write column switches to be        conductive at different times.

Another aspect of the static semiconductor storage device of the presentinvention comprises:

-   -   a plurality of word lines extended in a row direction;    -   a plurality of first bit lines extended in a column direction,        the plurality of first bit lines including i-th, j-th and k-th        first bit lines (i, j and k are different arbitrary positive        integers);    -   a plurality of pairs of second bit lines extended in the column        direction, the second bit lines including P-th and Q-th (P and Q        are different arbitrary positive integers) pairs of second bit        lines corresponding to a set of the i-th and j-th first bit        lines, and R-th and S-th (R and S are different arbitrary        positive integers) pairs of second bit lines corresponding to a        set of the j-th and k-th first bit lines;    -   a plurality of memory cells respectively arrayed in the row and        column directions and connected to the word lines by each row        and to the pairs of second bit lines by each column, each of the        memory cells having a plurality of transistors cross connected;    -   P-th to S-th sense amplifiers being used for single-end sensing,        each of the sense amplifiers having an input terminal connected        to one of each pair of the second bit lines;    -   a plurality of column selection switches respectively connected        between the sense amplifiers and the first bit lines, the column        selection switches including P-th and Q-th column selection        switches respectively connected between output terminals of the        P-th and Q-th sense amplifiers and the i-th first bit line, and        the column selection switches further including R-th and S-th        column selection switches respectively connected between output        terminals of the R-th and S-th sense amplifiers and the j-th        first bit line;    -   a plurality of pairs of write column switches respectively        connected between the first bit lines and the pairs of second        bit lines, the write column switches including a P-th pair of        write column switches connected between the i-th first bit line        and one of the P-th pair of the second bit lines and between the        j-th first bit line and the other of the P-th pair of the second        bit lines, and the write column switches further including a        Q-th pair of write column switches connected between the i-th        first bit line and one of the Q-th pair of the second bit lines        and between the j-th first bit line and the other of the Q-th        pair of the second bit lines, the write column switches further        includig an R-th pair of write column switches connected between        the j-th first bit line and one of the R-th pair of the second        bit lines and between the k-th first bit line and the other of        the R-th pair of the second bit lines, and the write column        switches yet further including an S-th pair of write column        switches connected between the j-th first bit line and one of        the S-th pair of the second bit lines and between the k-th first        bit line and the other of the S-th pair of the second bit lines;    -   a write controller to control conduction of the plurality of        pairs of write column switches, the write controller including a        write controller which controls the P-th and Q-th pairs of write        column switches and the R-th and S-th pairs of write column        switches to be conductive at different times; and    -   a column selection controller to control conduction of the        plurality of column selection switches, the column selection        controller including a column selection controller which        controls the P-th and Q-th pairs of column selection switches to        be conductive at different times, and controls the R-th and S-th        column selection switches to be conductive at different

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the circuitry of an SRAM of the single-endsensing type according to a first embodiment of the present invention.

FIG. 2 is a diagram showing the circuitry of an SRAM of the single-endsensing type according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a representative part of the circuitry of anSRAM of the single-end sensing type according to a third embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention are described below with referenceto the drawings.

FIG. 1 shows the circuitry of an SRAM of a single-end sensing typeaccording to a first embodiment of the present invention.

A plurality of memory cells M₀₀ to M_(mn) are arrayed in rows andcolumns on a semiconductor substrate (not shown). These memory cells M₀₀to M_(mn) are disposed at each intersection of rows. LA₀ to LA_(n) andcolumns CA₀ to CA_(m). The symbols m and n are positive integers of 1 ormore.

On the semiconductor substrate, a plurality of word lines WL₀ to WL_(n)are provided in a row direction. An insulating layer is interposedbetween the word lines and the semiconductor substrate. A plurality oflocal bit lines BL₀ to BL_(m) and BR₀ to BR_(m), which are pairedrespectively, are provided in a column direction. Moreover, in thecolumn direction, a plurality of global bit lines GL₀ to GL_(m+1) areprovided.

From the left part of the diagram, a memory cell group M₀₀ to M_(0n) toa memory cell group M_(m0) to M_(mn) are disposed between and connectedto the pairs of local bit lines BL₀ to BL_(m) and BR₀ to BR_(m),respectively. These pairs of local bit lines BL₀ to BL_(m) and BR₀ toBR_(m) are pulled up before readout.

Each memory cell M₀₀ to M_(mn) includes a flip-flop circuit FF and twon-channel switching transistors STr. Two p-channel transistors TrA andtwo n-channel transistors TrB constitute the flip-flop circuit FF.

Gate electrodes of switching transistors STr of each memory cell M₀₀ toM_(mn) are connected to word lines WL₀ to WL_(n), respectively.Switching transistors STr are conductive when the word lines are atlevel 1, and switching transistors STr are nonconductive when the wordlines are at level 0.

Local bit lines BL₀ to BL_(m) are connected to input terminals ofsingle-ended sense amplifiers A₀ to A_(m), respectively. Outputterminals of these single-ended sense amplifiers A₀ to A_(m), areconnected to global bit lines GL₀ to GL_(m), respectively. The globalbit lines are pulled up before readout.

Each single-ended sense amplifier A₀ to A_(m) includes one invertercircuit IV and first and second n-channel transistors Tr1 and Tr2.

Input signals from local bit lines BL₀ to BL_(m) are supplied toinverter circuit IV of each sense amplifier A₀ to A_(m). The outputs ofthese inverter circuits IV are supplied to gate electrodes of firstn-channel transistors Tr1. Drain electrodes of first n-channeltransistors Tr1 are connected to global bit lines GL₀ to GL_(m),respectively. Source electrodes of first n-channel transistors Tr1 areconnected to drain electrodes of second n-channel transistors Tr2.Source electrodes of second n-channel transistors Tr2 are earthed, andgate electrodes of second n-channel transistors Tr2 are supplied with anSAE signal.

When the SAE signal is level 1, second n-channel transistors Tr2 becomesconductive. Accordingly, single-ended sense amplifiers A₀ to A_(m) areenabled.

Herein, when local bit lines BL₀ to BL_(m) are at level 0, the output ofinverter circuit IV of each sense amplifier A₀ to A_(m) is at level 1.As a result, first n-channel transistors Tr1 become conductive. Thus,level 0 is read out from global bit lines GL₀ to GL_(m).

On the other hand, when local bit lines BL₀ to BL_(n) are at level 1,the output of inverter circuit IV of each sense amplifier A₀ to A_(m) isat level 0. As a result, first n-channel transistors Tr1 becomenonconductive. Thus, level 1 is read out from pulled-up global bit linesGL₀ to GL_(m).

Write column switches W₀₀ to W_(m0) are connected between local bitlines BL₀ to BL_(m) and global bit lines GL₀ to GL_(m).

Furthermore, local bit lines BR₀ to BR_(m) are connected to global bitlines GL₁ to GL_(m+1) located in the right adjacency in FIG. 1, throughwrite column switches W₀₁ to W_(m1).

A write controller 1 controls the pairs of write column switches W₀₀ toW_(m0) and W₀₁ to W_(m1) to be conductive at different times. Forexample, a pair of write column switches W₀₀ and W₀₁ in column CA₀ and apair of write column switches W₁₀ and W₁₁ in column CA₁ are controlledto be conductive at different times.

More specifically, gate electrodes of write column switches W₁₀ and W₁₁in column CA₁ are supplied with the least significant bit signal WE₁ ofa column address given from the outside, write controller 1. Inaddition, input signal WE₀, the inversion of signal WE₁, is supplied togate electrodes of write column switches W₀₀ and W₀₁ in column CA₀.

When a selected column is even, signals WE₁ and WE₀ become level 0 and1, respectively. On the contrary, when a selected column is odd, signalsWE₁ and WE₀ become level 1 and 0, respectively. In this way, it ispossible to control the write column switches in the adjacent column toconduct alternately without fail.

Next, when writing data into memory cell M₀₀ at column CA₀ and row LA₀,word line WL₀ is set to level 1 to make switching transistors STr ofmemory cell M₀₀ conductive. Since the least significant bit of thecolumn address given from the outside, write controller 1, is 0, signalWE₀ becomes level 1, and a pair of write column switches W₀₀ and W₀₁become conductive.

Consequently, global bit line GL₀ and memory cell M₀₀ are connectedthrough local bit line BL₀.

Moreover, global bit line GL₁ and memory cell M₀₀ are connected throughlocal bit line BR₀.

A pair of write column switches W₁₀ and W₁₁ becomes nonconductivebecause signal WE₁ is at level 0. Thus, global bit line GL₁ is notconnected to a memory group M₁₀ and M_(1n).

Accordingly, to write data into memory cell M₀₀, a level of eitherpulled-up global bit line GL₀ or global bit line GL₁ is reduced so thatlevels of a pair of local bit lines BL₀ and BR₀ can be controlled towrite data.

When global bit line GL₀ becomes level 0, local bit line BL₀ becomeslevel 0, and level 0 is stored in memory cell M₀₀. On the other hand,when global bit line GL₁ becomes level 0, local bit line BR₀ becomeslevel 0, and level 1 is stored in memory cell M₀₀.

The signals supplied to the gate electrodes of write column switches W₀₀to W_(m1) are not limited the least significant bit signal of the columnaddress given from the outside as described in the present embodiment.Write controller 1 may produce the signals to control adjacent pairs ofthe write column switches to be conductive at different times.

As described above, local bit lines BL₀ to BL_(m) and BR₀ to BR_(m)which are paired respectively, and adjacent pairs of global bit linesGL₀ to GL_(m+1), are used for the memory cell groups in columns CA₀ toCA_(m). Data stored in memory cells M₀₀ to M_(mn) can be effectivelyread out at global bit lines GL₀ to GL_(m) from local bit lines BL₀ toBL_(m) through sense amplifiers A₀ to A_(m).

When writing data into memory cells M₀₀ to M_(mn), global bit lineconnected to a selected memory cell and global bit line connected to thememory cell in the adjacent column are employed. Thus, a desirable datacan be written into the selected memory cell.

By sharing the global bit lines, it is possible to reduce the number ofglobal bit lines. In other words, the number of the wired global bitlines is approximately half of that in a conventional semiconductorstorage device, and it is possible to make pitches between the globalbit lines larger than those between the local bit lines. Moreover,capacitance or resistance per unit length of the global bit lines isreduced, so that high-speed operation of a semiconductor memory deviceis enabled.

FIG. 2 shows the circuitry of an SRAM of the single-end sensing typeaccording to a second embodiment of the present invention. The SRAM ofthe single-end sensing type in the second embodiment is a modificationexample of that in the first embodiment. Local bit lines BR₀ to BR_(m)are connected to the global bit lines in the nonadjacent columns.

Similar to the first embodiment, the second embodiment is provided withmemory cells M₀₀ to M_(mn), a plurality of paired local bit lines BL₀ toBL_(m) and BR₀ to BR_(m), a plurality of global bit lines GL₀ to GL_(m),single-ended sense amplifiers A₀ to A_(m), write column switches W₀₀ toW_(m1) and word lines WL₀ to WL_(n).

For example, as shown in FIG. 2, global bit line GL_(m) connected tolocal bit line BR₀ through write column switch W₀₁ is not a global bitline of right adjacent column CA₁, but is located in remote columnCA_(m) in the present embodiment (symbol m is a positive number of 2 ormore).

Signals generated at write controller 1 control the pair of write columnswitches W₀₀ and W₀₁ in column CA₀ and the pair of write column switchesW_(m0) and W_(m1) in column CA_(m) to be conductive at different times.

For instance, when writing data into memory cell M₀₀, a pair of writecolumn switches W₀₀ and W₀₁ in column CA₀ is set to be conductive, and apair of write column switches Wm₀ and W_(m1) in column CA_(m) is set tobe nonconductive.

As a result, global bit line GL₀ and memory cell M₀₀ are connectedthrough local bit line BL₀. Moreover, global bit line GL_(m) and memorycell M₀₀ are connected through local bit line BR₀.

Accordingly, by setting global bit line GL₀ being at level 0 andmaintaining the level of global bit line GL_(m) at a pulled-up level,local bit line BL₀ becomes level 0, and level 0 is stored in memory cellM₀₀. In addition, by maintaining the level of global bit line GL₀ at thepulled-up level and setting the global bit line GL_(m) being at level 0,local bit line BR₀ becomes level 0, and level 1 is stored in memory cellM₀₀.

As described above, although local bit line BR₀ is not connected toadjacent global bit line GL₁ but to global bit line GL_(m), it ispossible to write data into memory cell M₀₀.

Thus, similar to the first embodiment, the number of the wired globalbit lines is approximately half of that in the conventionalsemiconductor memory device. Consequently, pitches between the globalbit lines can be larger than those between the local bit lines.Furthermore, capacitance or resistance per unit length of the global bitlines is reduced, so that the high-speed operation of the semiconductorstorage device is enabled.

The local bit lines in other columns, besides the aforementioned columnCA₀, may also be connected to nonadjacent and remote global bit linesthrough the write column switches.

FIG. 3 shows a representative part of the circuitry of an SRAM of thesingle-end sensing type according to a third embodiment of the presentinvention.

Similar to the first embodiment, memory cells M₀₀ to M₃, in respectivecolumns CA₀ to CA₃ are connected to paired local bit lines BL₀ to BL₃and BR₀ to BR₃. The gate electrodes of switching transistors STrconstituting each memory cell are connected to word lines WL₀ to WL_(n).

Each local bit lines BL₀ to BL₃ are connected to input terminals ofsingle-ended sense amplifiers A₀ to A₃, respectively.

Output terminals of single-ended sense amplifiers A₀ and A₁ areconnected to global bit line GL₀ through column selection switches C₀₀and C₁₀, respectively. Furthermore, the output terminals of single-endedsense amplifiers A₂ and A₃ are connected to global bit line GL₂ throughcolumn selection switches C₂₀ and C₃₀, respectively.

On the left side of FIG. 3, write column switch W₀₀ and column selectionswitch C₀₀ are connected between local bit line BL₀ and global bit lineGL₀. Moreover, write column switch W₁₀ and column selection switch C₁₀are connected between adjacent local bit line BL₁ and global bit lineGL₀.

On the left side of FIG. 3, local bit line BR₀ is connected to globalbit line GL₂ through write column switch W₀₁ and column selection switchC₀₁. In addition, adjacent local bit line BR₁ is connected to global bitline GL₂ through write column switch W₁₁ and column selection switchC₁₁.

On the right side of FIG. 3, write column switch W₂₀ and columnselection switch C₂₀ are connected between local bit line BL₂ and globalbit line GL₂. Furthermore, write column switch W₃₀ and column selectionswitch C₃₀ are connected between adjacent local bit line BL₃ and globalbit line GL₂.

Moreover, local bit line BR₂ on the right side of FIG. 3 is connected toglobal bit line GL₄ through write column switch W₂₁, and columnselection switch C₂₁. In addition, adjacent local bit line BR₃ isconnected to global bit line GL₄ through write column switch W₃₁ andcolumn selection switch C₃₁.

As described above, global bit line GL₀ is shared by memory cells M₀₀ toM_(0n) and M₁₀ to M_(1n) located in two columns CA₀ and CA₁.Accordingly, a column of the memory cells, which data is read out fromor written into, is selected by inserting a write column switch and acolumn selection switch between global bit line GL₀ and local bit lineBL₀, and between global bit line GL₀ and local bit line BL₁,respectively.

Moreover, local bit lines BR₀ and BR₁ in columns CA₀ and CA₁ areconnected to global bit line GL₂ through the write column switches andthe column selection switch. This global bit line GL₂ is shared bymemory cells M₂₀ to M_(2n) and M₃₀ to M_(3n) located in other columnsCA₂ and CA₃. A column of the memory cells, which data is read out fromor written into, is selected by inserting a write column switch and acolumn selection switch between global bit line GL₂ and local bit lineBL₂ in column CA₂, and between global bit line GL₂ and local bit lineBL₃ in column CA₃, respectively.

In other words, global bit line GL₂ is shared by memory cells M₀₀ toM_(0n), M₁₀ to M_(1n), M₂₀ to M_(2n) and M₃₀ to M_(3n) located in therespective four columns CA₀, CA₁, CA₂ and CA₃.

A column selection signal CS₀ is supplied to gate electrodes of a pairof column selection switches C₀₀ and C₀₁ in column CA₀. Moreover, acolumn selection signal CS₁ is supplied to gate electrodes of a pair ofcolumn selection switches C₁₀ and C₁₁ in column CA₁.

In FIG. 3, n-channel transistors constitute column selection switchesC₀₀ to C₃₁. A signal generated at a column selection controller 2controls column selection signals CS₀ and CS₁ so as not to be at level 1simultaneously. When selecting a memory cell in column CA₀, CS₀ is setto be at level 1, and CS₁ is set to be at level 0. When selecting amemory cell in column CA₁, CS₀ is set to be at level 0, and CS₁ is setto be at level 1. For example, when the least significant bit signal ofthe column address given from the outside of column selection controller2 is set as CS₁ and the inverted signal of CS1 is set as CS₀, it ispossible to control column selection switches C₀₀ to C₃₁.

Furthermore, memory cells M₂₀ to M_(2n) and M₃₀ to M_(3n) located inadjacent columns CA₂ and CA₃ are similarly connected to single-endedsense amplifiers A₂ and A₃, respectively. Memory cells M₂₀ to M_(2n) andM₃₀ to M_(3n) are also connected to a pair of local bit lines BL₂ andBR₂ and a pair of local bit lines BL₃ and BR₃, respectively.

Write column switch W₂₀ is connected between single-ended senseamplifier A₂ and local bit line BL₂ in column CA₂.

Moreover, write column switch W₃₀ is connected between single-endedsense amplifier A₃ and local bit line BL₃ in adjacent column CA₃.

Further, local bit line BR₂ in column CA₂ is connected to global bitline GL₄ through write column switch W₂₁ and column selection switchC₂₁.

Furthermore, local bit line BR₃ in column CA₃ is connected to global bitline GL₄ through write column switch W₃₁ and column selection switchC₃₁.

Column selection controller 2 supplies a pair of column selectionswitches C₂₀ and C₂₁ with a column selection signal CS₀. In addition,column selection controller 2 supplies a pair of column selectionswitches C₃₀ and C₃, with a column selection signal CS₁.

The gate electrodes of a pair of write column switches W₀₀ and W₀₁ incolumn CA₀ and a pair of write column switches W₁₀ and W₁₁ in column CA₁are supplied with inverted signals WE₀ of the second least significantbit signals of column addresses given from the outside of writecontroller 1. The gate electrodes of a pair of write column switches W₂₀and W₂₁ in column CA₂ and a pair of write column switches W₃₀ and W₃₁ incolumn CA₃ are supplied with the second least significant bit signalsWE₁ of the column addresses given from the outside of write controller1. Thus, the write column switches in columns CA₀ and CA₁ and the writecolumn switches in columns CA₂ and CA₃ become conductive alternately.

When writing data into memory cell M₀₀ at column CA₀ and row LA₀, wordline WL₀ is set to level 1 to switch transistors STr of memory cell M₀₀to be conductive.

Since the second least significant bit of the column address given fromthe outside is 0, signal WE₀ is set to level 1. Accordingly, a pair ofwrite column switches W₀₀ and W₀₁ become conductive.

As a result, global bit line GL₀ and memory cell M₀₀ are connectedthrough local bit line BL₀ in column CA₀.

Furthermore, global bit line GL₂ and memory cell M₀₀ are connectedthrough local bit line BR₀ in column CA₀.

Write column switches W₂₀, W₂₁, W₃₀ and W₃₁ are nonconductive becausesignal WE₁ is at level 0. Hence, global bit line GL₂ is not connected tomemory cells M₂₀ to M_(2n) and M₃₀ to M_(3n) in columns CA₂ and CA₃.

Thus, to write data into memory cell M₀₀, either global bit line GL₀ orGL₂ is set to be at level 0. Consequently, levels of a pair of local bitlines BL₀ and BR₀ in column CA₀ can be controlled.

When global bit line GL₀ is set to be at level 0, local bit line BL₀becomes level 0, and level 0 is stored in memory cell M₀₀. Meanwhile,when global bit line GL₂ is set to be at level 0, local bit line BR₀ incolumn CA₀ becomes level 0, and level 1 is stored in memory cell M₀₀.

The same steps are applied when writing data into a memory cell in othercolumn.

In the third embodiment, global bit line GL₂ is shared by four pairs oflocal bit lines in the present embodiment. However, the number of thepairs is not limited to this. Five or more pairs of local bit lines mayshare one global bit line. In this case, division of time that theglobal bit line is used by each pair of local bit lines is required tobe increased.

In the present embodiment, three global bit lines are sufficient formemory cells in four or more columns. Thus, it is possible to reduce thenumber of the wired global bit lines further than the aforementionedfirst and second embodiments.

Accordingly, pitches between the wired global bit lines can be furtherincreased. Moreover, capacitance or resistance per unit length of theglobal bit lines is reduced so that the high-speed operation of thesemiconductor storage device is enabled.

Although the case of four columns CA₀ to Ca₃ is shown in FIG. 3, it ispossible to increase the number of the columns by forming the samecircuitry repeatedly.

As previously mentioned in the first to third embodiments, controlsignals for write column switches or column selection switches aregenerated from a column address given from the outside. However, thesignals are not limited to this. It is also possible to control thewrite column switches and the column selection switches by othersignals.

Moreover, the constituents of the memory cell are not limited to sixtransistors. For example, two resistors and two transistors mayconstitute a flip-flop circuit, and a pair of transistors may be crossconnected in a memory cell.

Furthermore, positional relationships between the pairs of local bitlines and the global bit lines may be formed on the same wiring layer ordifferent wiring layers in a semiconductor substrate. When positionalrelationships between the local bit lines and the global bit lines areformed on different wiring layers, it is possible to increase thepitches between the lines. Therefore, effects of the present inventioncan be further obtained.

Numerous modifications and variations of the present invention arepossible in light of the above teachings. It is therefore to beunderstood that, within the scope of the appended claims, the presentinvention can be practiced in a manner other than as specificallydescribed herein.

1. A static semiconductor storage device comprising: a plurality of wordlines extended in a row direction; a plurality of first bit linesextended in a column direction, the plurality of first bit linesincluding i-th, j-th and k-th first bit lines (i, j and k are differentarbitrary positive integers); a plurality of pairs of second bit linesextended in the column direction, the second bit lines including i-th,j-th and k-th pairs of second bit lines respectively corresponding tothe first bit lines; a plurality of memory cells respectively arrayed inthe row and column directions and connected to the word lines by eachrow and to the pairs of second bit lines by each column, each of thememory cells having a plurality of transistors cross connected; aplurality of sense amplifiers being used for single-end sensing, each ofthe sense amplifiers having an input terminal connected to one of eachpair of the second bit lines, and having an output terminal connected toeach of the first bit lines; a plurality of pairs of write columnswitches respectively connected between the first bit lines and thepairs of second bit lines, the write column switches including an i-thpair of write column switches connected between the i-th first bit lineand one of the i-th pair of the second bit lines corresponding to thei-th first bit line, and between the j-th first bit line and the otherof the i-th pair of the second bit lines and the write column switchesfurther including a j-th pair of write column switches connected betweenthe j-th first bit line and one of the j-th pair of the second bit linescorresponding to the j-th first bit line, and between the k-th first bitline and the other of the j-th pair of the second bit lines; and a writecontroller to control conduction of the plurality of pairs of the writecolumn switches, the write controller including a write controller tocontrol the i-th pair of write column switches and the j-th pair ofwrite column switches to be conductive at different times.
 2. A staticsemiconductor storage device comprising: a plurality of word linesextended in a row direction; a plurality of first bit lines extended ina column direction, the plurality of first bit lines including i-th,j-th and k-th first bit lines (i, j and k are different arbitrarypositive integers); a plurality of pairs of second bit lines extended inthe column direction, the second bit lines including P-th and Q-th (Pand Q are different arbitrary positive integers) pairs of second bitlines corresponding to a set of the i-th and j-th first bit lines, andR-th and S-th (R and S are different arbitrary positive integers) pairsof second bit lines corresponding to a set of the j-th and k-th firstbit lines; a plurality of memory cells respectively arrayed in the rowand column directions and connected to the word lines by each row and tothe pairs of second bit lines by each column, each of the memory cellshaving a plurality of transistors cross connected; P-th to S-th senseamplifiers being used for single-end sensing, each of the senseamplifiers having an input terminal connected to one of each pair of thesecond bit lines; a plurality of column selection switches respectivelyconnected between the sense amplifiers and the first bit lines, thecolumn selection switches including P-th and Q-th column selectionswitches respectively connected between output terminals of the P-th andQ-th sense amplifiers and the i-th first bit line, and the columnselection switches further including R-th and S-th column selectionswitches respectively connected between output terminals of the R-th andS-th sense amplifiers and the j-th first bit line; a plurality of pairsof write column switches respectively connected between the first bitlines and the pairs of second bit lines, the write column switchesincluding a P-th pair of write column switches connected between thei-th first bit line and one of the P-th pair of the second bit lines andbetween the j-th first bit line and the other of the P-th pair of thesecond bit lines, and the write column switches further including a Q-thpair of write column switches connected between the i-th first bit lineand one of the Q-th pair of the second bit lines and between the j-thfirst bit line and the other of the Q-th pair of the second bit lines,the write column switches further includig an R-th pair of write columnswitches connected between the j-th first bit line and one of the R-thpair of the second bit lines and between the k-th first bit line and theother of the R-th pair of the second bit lines, and the write columnswitches yet further including an S-th pair of write column switchesconnected between the j-th first bit line and one of the S-th pair ofthe second bit lines and between the k-th first bit line and the otherof the S-th pair of the second bit lines; a write controller to controlconduction of the plurality of pairs of write column switches, the writecontroller including a write controller which controls the P-th and Q-thpairs of write column switches and the R-th and S-th pairs of writecolumn switches to be conductive at different times; and a columnselection controller to control conduction of the plurality of columnselection switches, the column selection controller including a columnselection controller which controls the P-th and Q-th pairs of columnselection switches to be conductive at different times, and controls theR-th and S-th column selection switches to be conductive at differenttime.
 3. The static semiconductor storage device according to claim 1,wherein the i-th and j-th first bit lines are complementary data linesof the memory cells connected to the i-th pair of second bit lines, andthe j-th and k-th first bit lines are complementary data lines of thememory cells connected to the j-th pair of second bit lines.
 4. Thestatic semiconductor storage device according to claim 2, wherein thei-th and j-th first bit lines are complementary data lines of the memorycells connected to the P-th and Q-th pairs of second bit lines, and theJ-th and k-th first bit lines are complementary data lines of the memorycells connected to the R-th and S-th pairs of second bit lines.
 5. Thestatic semiconductor storage device according to claim 1, wherein thesense amplifiers are constituted by logic gates.
 6. The staticsemiconductor storage device according to claim 2, wherein the senseamplifiers are constituted by logic gates.
 7. The static semiconductorstorage device according to claim 1, wherein at least two of the i-th tok-th first bit lines are adjacent to each other.
 8. The staticsemiconductor storage device according to claim 2, wherein at least twoof the i-th to k-th first bit lines are adjacent to each other.
 9. Thestatic semiconductor storage device according to claim 1, wherein thej-th first bit line is adjacent to both the i-th and k-th first bitlines.
 10. The static semiconductor storage device according to claim 2,wherein the j-th first bit line is adjacent to both the i-th and k-thfirst bit lines.
 11. The static semiconductor storage device accordingto claim 1, wherein an l-th (1 is a positive integer different from iand j) first bit line is disposed between the i-th first bit line andthe j-th first bit line.
 12. The static semiconductor storage deviceaccording to claim 2, wherein an l-th (1 is a positive integer differentfrom i and j) first bit line is disposed between the i-th first bit lineand the j-th first bit line.
 13. The static semiconductor storage deviceaccording to claim 1, wherein a wiring layer of the first bit lines isdifferent from a wiring layer of the second bit lines.
 14. The staticsemiconductor storage device according to claim 2, wherein a wiringlayer of the first bit lines is different from a wiring layer of thesecond bit lines.
 15. The static semiconductor storage device accordingto claim 1, wherein resistance per unit length of the first bit lines islower than that of the second bit lines.
 16. The static semiconductorstorage device according to claim 2, wherein resistance per unit lengthof the first bit lines is lower than that of the second bit lines. 17.The static semiconductor storage device according to claim 1, whereincapacitance per unit length of the first bit lines is lower than that ofthe second bit lines.
 18. The static semiconductor storage deviceaccording to claim 2, wherein capacitance per unit length of the firstbit lines is lower than that of the second bit lines.
 19. The staticsemiconductor storage device according to claim 1, wherein the writecontroller generates a predetermined bit signal of a column address andan inversion signal of the bit signal.
 20. The static semiconductorstorage device according to claim 2, wherein the write controllergenerates a predetermined bit signal of a column address and aninversion signal of the bit signal.
 21. The static semiconductor storagedevice according to claim 1, wherein the column selection controllergenerates a predetermined bit signal of a column address and aninversion signal.
 22. The static semiconductor storage device accordingto claim 2, wherein the column selection controller generates a signalof a column address and an inversion signal of the bit signal.